Budapest University of Technology and Economics, Faculty of Electrical Engineering and Informatics

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    Digital Design

    A tantárgy neve magyarul / Name of the subject in Hungarian: Digitális technika

    Last updated: 2015. február 13.

    Budapest University of Technology and Economics
    Faculty of Electrical Engineering and Informatics
    Engineering Information Technology, BSc

    Course ID Semester Assessment Credit Tantárgyfélév
    VIMIAA01 1 3/1/2/V 7  
    3. Course coordinator and department Dr. Fehér Béla,
    Web page of the course
    4. Instructors

    Dr. Béla Fehér, MIT

    Dr. Zoltán Benesóczky, MIT  

    5. Required knowledge -
    6. Pre-requisites
    NEM (TárgyEredmény("BMEVIMIA111", "jegy", _) >= 2
    TárgyEredmény("BMEVIMIA111", "felvétel", AktualisFelev()) > 0
    TárgyEredmény("BMEVIMIAA02", "jegy", _) >= 2
    TárgyEredmény("BMEVIMIAA02", "felvétel", AktualisFelev()) > 0
    TárgyEredmény( "BMEVIMIAA02" , "aláírás" , _ ) = -1)

    A fenti forma a Neptun sajátja, ezen technikai okokból nem változtattunk.

    A kötelező előtanulmányi rendek grafikus formában itt láthatók.

    7. Objectives, learning outcomes and obtained knowledge

    Digital technology is an important core subject in the curriculum of the Engineering Information Technology, and the most important objective of the course to present the process of engineering and system-oriented approach of problems and the required basic practical skills, to establish good problem solving skills. The following topics are discussed: computing systems, the basic elements of the operation of logic circuits, the digital abstraction of the simple tasks and direct hardware or low-level software implementations of them.

    The course starts with the introduction of the binary arithmetic, the operations done by basic digital functional units and controllers, and ending by the presentation of the general-purpose microcontroller architecture and its design and applications. Lectures are completed with classroom and laboratory exercises, where the focus is on the mastering of modern computer design methods and the direct design/development experience.

    8. Synopsis

    1.      LEC1: Introduction to the world of digital technology. Hierarchical approach: System - Module - Gate / FF - Primary switch. The design (synthesis) and verification (analysis) of the system operation. Analog and digital signals. Conversion, quantization, discrete values​​. The digital representation: data formats, encoding, and information content. Number systems, number representations (integer, real, float) properties (range, resolution).


    EXC1: Number systems, codes, code conversion (BIN2BCD, BCD2BIN). Binary arithmetic.


    LAB1: Tools, presentation of CAD environment. Basics of Verilog HDL language description (modules, input, output, functional details). Creation of the first project (SWITCH → LEDs)



    2.      LEC2: Boolean algebra. Logic functions, combinatorial networks. Specification, representation, conversion and clarity of specification. Basic elements, gates, two level networks, SOP realization. Minimization algorithms. Handling and exploitation of don’t care specifications. Multi-level networks, global optimization issues.


    EXC2: Working with Logic Functions (specification, simplification, realization). Simple examples, like one -bit adder, decoder (N → 2N), encoder (2N → N).


    LAB2: Using Verilog HDL design of combinatorial logic. Design of elementary logical functions of 3-4 variables. Check of a 4-bit BCD value. Identification of 4-bit values for 3 to 5 divisibility. Cascade 4-bit adder design. 3/8 decoder and 8/3 encoder design.


    3.      LEC3: Technology details of digital devices: elementary switches, CMOS transistors. The operation of an inverter, the basic structures of gates. Signal levels and output types (normal, HiZ, OC). Universal circuits, the homogeneous realization: NAND/NOR, MUX and LUT based designs. Realization of bit storage functions. The edge-triggered DFF, as synchronous sampling element. The multi-bit register. The basic resources of the configurable FPGA: logic cell (LUT + DFF), I/O cell (DFF + HiZ I/O), wiring (switches) and the SRAM memory cell (configuration memory).


    EXC3: The use of standard combinatorial functions: extensibility, cascade (linear and tree topologies), additional inputs and outputs. Introduction of the functionality of the Enable inputs, in case of MUX and DEC.


    LAB3: Introduction of the 7-segment display. 4 input-7 output decoder design. Static (one digit) and dynamic (two digits) display design using the four-digit unit. BIN → BCD converter design 4-5-6 binary bits.


    4.      LEC4: Operating characteristics of the edge-triggered DFF: Synchronous timing parameters. HDL language modeling of the synchronous operation. The general sequential logic. FSM models, state register, the state transition function and the output functions. Specification methodologies: state diagram, state table. HDL-based specification FSM specification style, combined and separated description.


    EXC4: Creating of the state diagram for simple sequential networks. HDL design specification based on the general FSM model.


    LAB4: FSM design of a 4-bit code transmitter with fixed and adjustable codes. Analysis of the operation using the simulation waveform. Design of a 4-bit pattern recognizer FSM for fixed and adjustable codes.



    5.      LEC5: State minimization principles and methods. State coding, and its effect on the FSM complexity. Treatment of non-defined conditions. The general structure of multi-function registers, deriving of control functions. Examples: SHR, CNT. Basic functions: Reset, Load, Enable, and Direction select. Encoded and decoded control. The general structure of the HDL model and it’s built in priority.


    EXC5: Design of a general purpose shift register. Interface signals, control signals. Cascading of SHR-s. SHR-based counters. Binary counters. BCD counters.


    LAB5: SHR-based counters. Structure of a 4-digit 7-segment display unit. Design of a BCD counter unit and construction of a 4-digit counter chain.



    6.      LEC6: Combinatorial and sequential components. Designing of data-processing units, examples of simple tasks. Properties of counters, utilization of CNTs in timing and control tasks. Programmable logic elements, PLD, FPGA. Memory: RAM, ROM. Synchronous memory circuits within the FPGA. HDL specification templates.


    EXC6: Usage of memory devices. Creation of an NxM memory unit from nxm sized blocks. Address, data and control lines. Read/write operations. Overview of the SRAM memory control circuit functions overview.


    LAB6: Design of a data search unit 256-byte ROM memory. Specification: Find a data byte with given properties. Display the result on the 4-digit display unit, as {address, data}.


    7.      EA7: The register transfer level (RTL) design methodology. Specification of control and data processing units. Task-specific solutions in the design process.


    EXC7: Digital system design: The greatest common divisor (GCD). Overview of the algorithm. Specification of the required data processing units and control signals. The state diagram of the controller and the design of the FSM.


    LAB7: Design of the GCD unit using HDL code. Simulation and implementation.


    8.      LEC8: Controllers, the ASM approach. Elements of operations, management conditions. State transitions, control structures. The micro-programmed control unit. Address register, selection criteria, control commands (CONT, JMP, CJP (cond)). The micro-structure of instruction. The generalized data processing unit. Input and output interfaces, internal storage units. Data size, standardized operations. The elements of the data structure: memory, registers/register array, stack, ALU status flags.


    EXC8: The GCD task realization with micro-programmed control. Specification of microinstructions, organization of control signals.


    LAB8: The HDL specification of the micro-programmed control.


    9.      LEC9: Introduction of the microcontroller/microprocessor. Program memory, program counter, instruction execution phases: F-D-E. The FSM model of the instruction execution. The instruction architecture (IA), types of instruction formats: 0R, 1R, 2R, 3R. Main features of the RISC/CISC style CPUs. Instruction Set analysis, operand access, addressing modes. Machine- level programming, machine code, mnemonic, simple demo program.


    EXC9: The MiniRISC CPU architecture, block diagram. The MiniRISC machine code programming, coding of 2-3 simple program (max. 10-20 instructions!)


    LAB9: Introduction of the MiniRISC GUI. Development of applications: source code editing, translation, download, run. Debug functions.


    10.  LEC10: The microprocessor bus. Address, data and control signals. Features of buses: bus cycle concept, synchronous/asynchronous flow control, master/slave units, arbitration. Peripheral management concept, basic operations: address decoding, command signal generation, synchronization/acknowledgement return. Bus interface logic elements: data registers, command/status registers. The operation of the user logic and its monitoring. Peripheral management tasks: reset, mode setting, start. Peripheral management using polling or interrupt (IRQ).


    EXC10: Design of an input (switch, push button) and output (LED) peripheral interface. Address decoder, command signal generator, bus drivers.


    LAB10: Peripheral management using polling for LED brightness control.


    11.  LEC11: Typical peripheral units in microcontrollers: the GPIO peripheral. General role, circuit structure, typical services, usage. IN/OUT/INOUT configurations. The Timer unit. Function, circuit structure, typical services, usage. Time measurement, timing schedule, periodic waveforms.


    EXC11: Micro servo motor control. Control waveform specification of -90 °, 0 ° , + 90 ° settings. User specification: 2 -digit BCD value, plus sign.


    LAB11: Programmed micro servo motor control. Design of PWM using timer-based control, of the GPIO interface.


    12.  EA12 12: Introduction of the interrupt. Operational phases of the CPU in case of interrupt. IRQ enable, IRQ acknowledge, IRQ service routine. Interrupt systems (simple, vector, one-level, multi-level, priority management).


    EXC12: Design of a digital clock with HHMM display, alarm function, timer function. Program structure with interrupt handling.


    LAB12: Microprocessor based clock with special functions.


    13.  LEC13: Basic serial communication interfaces: UART/USRT, SPI. The design options of external buses. Autonomous data transfer units, features of direct memory access (DMA).


    EXC13: Review of a simple DMA peripheral unit. Overview of functions, usage of mode registers. Analysis of the operation, evaluation of data transfer rate.


    LAB13: Data block copy from the memory to the PC terminal through the USRT peripheral using DMA.


    14.  LEC14: Overview of topics of the course. The role of digital technology in embedded systems.  Joint management of HW-SW during system implementation. Designing complex hierarchical systems.


    EXC14: -


    LAB14: - 


    10. Assessment

    During the study period:

    The participation on the lectures, classroom exercises and laboratory practice is compulsory. Checking the presence on the lectures is provided electronically, on the exercises and lab sessions personally. Student who is missing more than 30% of lectures or classroom exercises, will not get the signature about the semester. Missing more than two laboratory practice will also invalidate the semester.

    During the study period, students will perform a midterm 1 (max. 60 points) and submit 2 individually prepared homework (2x15 points). During the laboratory work they can earn 1-1 point in every week.


    Above the attendance requirements, the signature at the end of the semester needs at least of 40 points performance from the midterm, homework and laboratory work.


    The examination period:

    The course will offer the written examination. Final mark will be calculation is based in 75% by the result of the written exam and 25% on the achieved mid-term score. For successful result the required minimum pass grade is 40 % in the written examination. 
    11. Recaps

    During the semester and the additional week an extra midterm opportunity provided. During the semester, and the additional week one-one laboratory work can be re-executed.

    12. Consultations

    Instructors will offer consultation possibility, in case of demand.

    13. References, textbooks and resources

    Frank Vahid: Digital Design, John Wiley & Sons, 2007, (ISBN 978-0-470-04437-7)

    Milos Ercegovac, Tomás Lang, Jaime H. Moreno: Introduction to Digitla Systems, John Wiley & Sons, 1999, (ISBN 0-471-57299-8)

    Richard S. Sandige: Digital Desig Essentials, Prentice Hall, 2002, (ISBN 0-201-47689-4)

    David Money Harris, Sarah L. Harris: Digital Design and Computer Architectures, Elsevier, 2013, (ISBN 978-0-12-394424-5)Linda Null, Julia Lobur: Computer Organization and Architecture, Jones &Bartlett Learning, 2014, ISBN-13: 9781284045611


    The lecture presentation outlines are available:

    14. Required learning hours and assignment
    Contact hours84
    Study during the semester42
    Preparation of midterm14
    Preparation of homework40
    Assigned written material
    Preparation of exam30
    15. Syllabus prepared by Dr. Béla Fehér, Associate Professor, MIT