Budapest University of Technology and Economics, Faculty of Electrical Engineering and Informatics

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    Digital Design 1

    A tantárgy neve magyarul / Name of the subject in Hungarian: Digitális technika 1

    Last updated: 2021. szeptember 3.

    Budapest University of Technology and Economics
    Faculty of Electrical Engineering and Informatics
    Course ID Semester Assessment Credit Tantárgyfélév
    VIIIAA04 1 3/1/1/v 6  
    3. Course coordinator and department Dr. Pilászy György,
    Web page of the course https://www.iit.bme.hu/targyak/BMEVIIIAA04
    4. Instructors

    Dr. István Horváth

    Dr. György Rácz 

    6. Pre-requisites
    Kötelező:
    NEM (TárgyEredmény( "BMEVIIIA104", "jegy" , _ ) >= 2
    VAGY TárgyEredmény("BMEVIIIA104", "FELVETEL", AktualisFelev()) > 0
    VAGY TárgyEredmény( "BMEVIIIA105", "jegy" , _ ) >= 2
    VAGY TárgyEredmény("BMEVIIIA105", "FELVETEL", AktualisFelev()) > 0
    VAGY TárgyEredmény( "BMEVIIIAA01", "jegy" , _ ) >= 2
    VAGY TárgyEredmény("BMEVIIIAA01", "FELVETEL", AktualisFelev()) > 0
    VAGY TárgyEredmény( "BMEVIIIAA01" , "aláírás" , _ ) = -1 )

    ÉS (Training.Code=("5N-A7") VAGY Training.Code=("5N-A7H") VAGY Training.Code=("5NAA7"))

    A fenti forma a Neptun sajátja, ezen technikai okokból nem változtattunk.

    A kötelező előtanulmányi rendek grafikus formában itt láthatók.

    7. Objectives, learning outcomes and obtained knowledge

    The aim of the course (together with the course entitled Digital Design 2) is to provide the students with all the basic system level hardware knowledge that is required to the logical level design and understanding of digital equipment. In order to raise awareness to practical design problems, the theoretical background is extended trough classroom practices. Students can try their obtained skills in several laboratory sessions.

    Students successfully passing the course will:

    • know the main digital circuit building blocks from the user’s perspective,
    • learn the design steps of combinational and sequential logical systems,
    • learn how to identify and eliminate hazards and race conditions,
    • be able to solve all the basic logical design problems they may encounter in electrical engineering
    8. Synopsis

    Basic logic design principles. Analog versus digital signal processing. Logical systems as theoretical abstractions of digital equipment. Boole algebra and number systems. Arithmetical operations in different number systems.

    Basic models and properties of combinational and sequential systems. Truth-table representation of combinational systems. Switching functions, disjunctive and conjunctive canonical forms. Expressing canonical forms based on the truth table.

    Building blocks of combinational systems (gates) and their theoretical modeling with switching functions. Logic circuit diagrams. Disjunctive and conjunctive minimal two-level realizations of switching functions.

    Basic concepts and usage of the Verilog hardware description language.

    Minimization of switching functions using the Karnaugh map. Concept of the prime implicant. Finding disjunctive and conjunctive minimal two-level realizations on the Karnaugh map. Essential prime implicants.

    Optimal cover algorithm for selection from prime implicants. Petrick’s method. Handling don’t care terms. Multiple-output minimization.

    Special problems of symmetric switching functions. Practical minimization problems. Canonical forms of symmetric switching functions.

    Transient behavior and timing of combinational systems, causes and components of signal delays. Static, dynamic and functional hazards and their elimination. Designing the minimal two-level hazard-free realization.

    Special problems of multilevel combinational systems. Applying an already existing building block in the design.

    Classification of sequential systems as state machines (asynchronous and synchronous realizations, Mealy- and Moore-models). State table and state diagram. Analyzing sequential systems. Flip-flops as building blocks (SR, JL, T, DG and D flip-flops). Realizing flip-flops with other flip-flops.

    Design steps of synchronous state machines (constructing the preliminary state table, state assignment). Finding the minimal realizations of the control switching functions. Effect of the state assignment on the complexity of the resulting system.

    Special problems with the design of asynchronous state machines. Metastable states. Practical realization of a D flip-flop, designed as an asynchronous state machine.

    Clock skew and its elimination by applying data-lock-out flip-flops. Practical realization of flip-flops. (simple edge-triggered, master-slave, data-lock-out structures).

    State reduction methods on fully specified state tables. Properties of equivalent states, filling the state equivalence table. Creating the reduced state table.

    State reduction methods on not fully specified state tables (containing don’t care outputs or transitions). Properties of compatible states. Practical problems of systematically finding the minimal number of states.

    Analyzing synchronous sequential networks.

    Applying MSI chips for designing functional units. Multiplexers, demultiplexers, decoders counters, shift registers, arithmetic units and comparators.

    Topics of the laboratory practices:

    1. Analyzing combinational networks
      Finding the truth table of an already realized combinational system.
      Design and implementation of a simple combinational network based on a given specification.
      Demonstrating hazards in a combinational system.
    2. Analyzing sequential networks 1.
      Analyzing two sequential systems performing the same function but based on different models (Mealy and Moore)
      Realizing a flip-flop with another flip-flop.
    3. Analyzing sequential networks 2.
      Demonstrating the effects of clock skew.
      Design and implementation of a simple sequential network based on a given specification.
    9. Method of instruction

    Three hours of lecture weekly, two hours of classroom practice every other week and altogether three times four hours laboratory practice.

    10. Assessment

    Attendance on at least 70% of the classroom practices and on all the laboratory practices is mandatory for passing the course.

    The term requirements are fulfilled by achieving at least 60% of all the points on the homework assignments.

    Written examination in the exam period.

    11. Recaps

    Only one laboratory practice can be repeated.

    13. References, textbooks and resources

    M. Morris Mano, Charles R. Kime: Logic and Computer Design Fundamentals, Prentice Hall, 2001, ISBN 0-13-031486-2

    John F. Wakerly: Digital Design, Prentice Hall, 2001, ISBN 0-13-089896-1

    14. Required learning hours and assignment
    Contact hours 70
    Preparation for contact hours 34
    Preparation for the midterm 0
    Homework assignments 16
    Home readings 10
    Preparation for the exam 50
    Total workload 180