Dr. Horváth Gábor    Associate processor    Department of Networked Systems and Services

Kötelező:

The objective of the course is to provide deep knowledge to the students on the internals, operation and properties of computers. Getting familiar with the characteristics of the hardware allows to develop efficient software that utilizes the computer’s resources as much as possible.

Introductory topics. Information processing models. Control driven architectures: Neumann, Harvard and modified Harvard architectures.

 

I/O devices. Dedicated I/O instructions vs memory mapped communication. Flow control. Processing the signals of the peripherals: polling, interrupt, interrupt in multi-processor environment, interrupt moderation. Decreasing the load of the CPU: DMA, I/O processor. I/O peripheral interconnects: busses, point-to-point connections, serial vs. parallel lines, timing, arbitrations. Systems with a single bus, multiple busses, south- and north bridge. PCI, PCI Express and USB peripheral interfaces.

Mass storage drives. The main operation of hard disk drives: sectors, zoned bit recording. Components of the delay of read and write requests. Command queueing. The physical operation of SSDs. Aging, data unit of operations, the unique implementation of the write requests. The tasks of the SSD controller: garbage collection, wear leveling, data compression, over-provisioning.

Memory systems. Synchronous DRAM based system memory: the role of the memory controller, memory modules, ranks, and banks. The DRAM commands and their timing, out-of-order scheduling of the commands. Virtual memory: address translation, TLB, page table implementations, single-level and multi-level page tables. Address space separation. Cache memory: the locality of references, cache organization, relation with the virtual memory. Cache content management: pollution avoidance, pre-fetch, block replacement algorithms. Locality aware programming techniques.

 

Processor.  Instruction set architectures, CISC and RISC strategies. Pipeline instruction processing. The hazards and their resolutions. The implementation details of a simple 5-stage instruction pipeline. Introducing multiple functional units with non-equal delay. Dynamic instruction scheduling (out-of-order execution). The precedence graph and the data-flow execution of the instructions. The role of the instruction window, register renaming and re-order buffer. The Tomasulo algorithm. Wide pipelines: superscalar, VLIW and EPIC architectures. Branch prediction: predicting the outcome and the target address of branches. Branch prediction aware programming.

 

Parallel processing. Data parallelism: vector processors, SIMD instructions, array processors. Multiprocessor systems: the notion of explicit parallelism, multi-threaded processors. Classification of multiprocessor systems. Cache coherence and memory consistency problems in shared memory multiprocessor systems.

Lectures: one lecture every week

Classroom practices: one practice every second week

There is one mid-term test during the semester, it has to be successfully accomplished in order to get the signature. 

To get the credit, a successful exam is required in the exam period.

It is possible to re-take the mid-term test in the last week of the semester and in the re-take week. 

Personal consultation with the lecturer is possible, appointment via e-mail.