Budapest University of Technology and Economics, Faculty of Electrical Engineering and Informatics

    címtáras azonosítással

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    Computer Architectures

    A tantárgy neve magyarul / Name of the subject in Hungarian: Számítógép-architektúrák

    Last updated: 2018. január 19.

    Budapest University of Technology and Economics
    Faculty of Electrical Engineering and Informatics
    Course ID Semester Assessment Credit Tantárgyfélév
    VIHIAA02   2/1/0/v 4  
    3. Course coordinator and department Dr. Horváth Gábor,
    4. Instructors
    Dr. Horváth Gábor    Associate processor    Department of Networked Systems and Services

    6. Pre-requisites
    VAGY TárgyTeljesítve("BMEVIMIAA02")
    VAGY TárgyTeljesítve("BMEVIMIA111") )

    ÉS NEM (TárgyEredmény("BMEVIHIA210", "jegy", _) >= 2
    TárgyEredmény("BMEVIHIA210", "felvétel", AktualisFelev()) > 0
    TárgyEredmény("BMEVIHIAA00", "jegy", _) >= 2
    TárgyEredmény("BMEVIHIAA00", "felvétel", AktualisFelev()) > 0
    TárgyEredmény( "BMEVIHIAA00" , "aláírás" , _ ) = -1)

    ÉS (Training.Code=("5N-A8") VAGY Training.Code=("5NAA8"))

    A fenti forma a Neptun sajátja, ezen technikai okokból nem változtattunk.

    A kötelező előtanulmányi rend az adott szak honlapján és képzési programjában található.

    7. Objectives, learning outcomes and obtained knowledge
    The objective of the course is to provide deep knowledge to the students on the internals, operation and properties of computers. Getting familiar with the characteristics of the hardware allows to develop efficient software that utilizes the computer’s resources as much as possible.

    8. Synopsis
    Introductory topics. Information processing models. Control driven architectures: Neumann, Harvard and modified Harvard architectures.
    I/O devices. Dedicated I/O instructions vs memory mapped communication. Flow control. Processing the signals of the peripherals: polling, interrupt, interrupt in multi-processor environment, interrupt moderation. Decreasing the load of the CPU: DMA, I/O processor. I/O peripheral interconnects: busses, point-to-point connections, serial vs. parallel lines, timing, arbitrations. Systems with a single bus, multiple busses, south- and north bridge. PCI, PCI Express and USB peripheral interfaces.

    Mass storage drives. The main operation of hard disk drives: sectors, zoned bit recording. Components of the delay of read and write requests. Command queueing. The physical operation of SSDs. Aging, data unit of operations, the unique implementation of the write requests. The tasks of the SSD controller: garbage collection, wear leveling, data compression, over-provisioning.

    Memory systems. Synchronous DRAM based system memory: the role of the memory controller, memory modules, ranks, and banks. The DRAM commands and their timing, out-of-order scheduling of the commands. Virtual memory: address translation, TLB, page table implementations, single-level and multi-level page tables. Address space separation. Cache memory: the locality of references, cache organization, relation with the virtual memory. Cache content management: pollution avoidance, pre-fetch, block replacement algorithms. Locality aware programming techniques.
    Processor.  Instruction set architectures, CISC and RISC strategies. Pipeline instruction processing. The hazards and their resolutions. The implementation details of a simple 5-stage instruction pipeline. Introducing multiple functional units with non-equal delay. Dynamic instruction scheduling (out-of-order execution). The precedence graph and the data-flow execution of the instructions. The role of the instruction window, register renaming and re-order buffer. The Tomasulo algorithm. Wide pipelines: superscalar, VLIW and EPIC architectures. Branch prediction: predicting the outcome and the target address of branches. Branch prediction aware programming.
    Parallel processing. Data parallelism: vector processors, SIMD instructions, array processors. Multiprocessor systems: the notion of explicit parallelism, multi-threaded processors. Classification of multiprocessor systems. Cache coherence and memory consistency problems in shared memory multiprocessor systems.

    For the practices:
    - Reviewing the digital design knowledge through a simple hardware-software design problem
    - I/O devices: CPU load computations with polling and interrupt-based I/O
    - Mass storage drives: HDD response time and throughput computations, SSD write management algorithms
    - Memory systems: DRAM command scheduling, delay computations, virtual memory exercises with and without TLB
    - Cache memory: Examples for cache organizations. Cache miss ration computations for small C programs, optimization.
    - Pipeline scheduling: Instruction scheduling for low level programs for particular pipelines, optimal instruction scheduling
    - Advanced pipeline techniques: Dependency analysis, eliminating anti-dependencies with register renaming. Optimizing for branch prediction in small C programs.

    9. Method of instruction
    Lectures: one lecture every week
    Classroom practices: one practice every second week

    10. Assessment
    There is one mid-term test during the semester, it has to be successfully accomplished in order to get the signature. 
    To get the credit, a successful exam is required in the exam period.
    11. Recaps
    It is possible to re-take the mid-term test in the last week of the semester and in the re-take week. 

    12. Consultations
    Personal consultation with the lecturer is possible, appointment via e-mail.

    13. References, textbooks and resources
    • Lecture slides
    • David A. Patterson, John L. Hennessy. Computer Organization and Design, Morgan Kaufmann Publishers, 2011.
    • Jean-Loup Baer. Microprocessor Architecture, Cambridge University Press, 2010.
    • Bruce Jacob, Spencer W. Ng, Samuel Rodriguez. Memory Systems, Morgan Kaufmann Publishers, 2008.
    • William Stallings. Computer Organization and Architecture, 2012.
    14. Required learning hours and assignment
    Kontakt óra42
    Félévközi készülés órákra22
    Felkészülés zárthelyire16
    Házi feladat elkészítése0
    Kijelölt írásos tananyag elsajátítása0
    15. Syllabus prepared by Dr. Horváth Gábor    Associate processor    Department of Networked Systems and Services