A kötelező előtanulmányi rend az adott szak honlapján és képzési programjában található.

Introduction: The alternatives of the system realization. The full custom system, the processor (controller) " firmware and the programable gate arrays.

Design methods: the top-down and the bottom-up style. Automatization, silicon compilers.

Simulation methods, software solutions 

System level modelling. Available harware modeling languages: SystemC, VHDL, Verilog, and Verilog-AMS.

The detailed study of the VHDL and Verilog languages.

The introduction to the SystemC and CatapultC languages. Design practices.

Challenges of the analogue and mixed mode simulation. The Verilog-AMS language.

The physical realization: ROM memory blocks, FPGA and FPLA matrices, microcontrollers, and ASIC.

The system synthesis for different technologies: FPGA, FPAA, FPMA, SiP and SoC.

Hardware-software co-design, VC (Virtual Component) and IP (Intellectual Property) bsed design.

Testing and verification. Design for testability(Dft).

3 hours/week lectures and computer based demonstration with examples.

a. In the class period: one midterm test.

Requirement for the signature: final mark >= 2 (satisfactory).

Final mark is based on the result of the mid-term test.

Threshold for satisfactory results: minimum 40% of the maximal score.

b. In the examination period: n.a.

c. Exam before the examination period: possible.

Handouts.

Optional: Giovanni de Micheli és Mariagiovanna Sami: „Hardware/software co-design” Kluwer Publisher 1996. ISBN 0-7923-3882-0